Semiconductor components usually comprise a semiconductor chip, in which an integrated microelectronic circuit is embodied, and a chip housing, which serves for externally driving the semiconductor chip and enables the semiconductor chip to be mounted on a superordinate electronic unit, for instance on an electronic printed circuit board (PCB) or else on a housing of a further semiconductor chip. Particularly on memory modules, the semiconductor components are usually no longer only arranged alongside one another directly on one or both main surfaces of the electronic printed circuit board, but are also stacked one above another, so that, on each surface region of the printed circuit board at which a semiconductor component is mounted, said semiconductor component carries one or more further semiconductor components. Consequently, on each surface region of the printed circuit board provided for semiconductor components, there is situated in each case a stack of a plurality of semiconductor components which are arranged one on top of another and which can be driven jointly by the printed circuit board of the memory module or of some other superordinate electronic unit.
The chip housings are often embodied as BGA housings (Ball Grid Array) which have, on their underside, two arrays of contact connections which can be mounted at a printed circuit board by means of soldering connections, and which have, in a central region on their top side, chip-side contact connections for making contact with the semiconductor chip. Within the chip housing, said connections are connected to the contact connections on the underside of the chip housing by means of conductor tracks. As a result, the semiconductor chip can be driven via the chip housing by an electronic printed circuit board or a further semiconductor component carrying the chip housing.
The chip housings, which are usually embodied mirror-symmetrically with respect to the housing frame, thus have a first region and a second region (approximately corresponding to the two housing frame halves provided with contact arrays on the underside) which extend laterally beyond a respective edge of the semiconductor chip. By way of example, a first region of the chip housing, which has a first arrangement of contact connections on its underside, extends in a positive x-direction beyond a first edge of the semiconductor chip, whereas another, second region of the chip housing having a further, second array of contact connections extends in a negative x direction beyond an opposite second edge of the semiconductor chip. The housing frame is embodied mirror-symmetrically with respect to the center between the two arrays of contact connections, and the semiconductor chip is generally arranged in the center between the two arrays of contact connections, but usually on the top side of the chip housing.
The conductor tracks running within the chip housing may comprise horizontal conductor track segments, that is to say conductor track segments running parallel to the top side and underside of the chip housing, and also vias, that is to say conductive contact hole fillings running perpendicular to the top side and underside. Usually, when viewed from outside, the construction of a BGA housing is mirror-symmetrical with respect to the center between the two edges of the semiconductor chip arranged on the chip housing. Thus, generally a pair of two arrays (or arrangements) of contact connections, which generally comprise the same number of contact connections, is provided on the underside of the chip housing. Accordingly, the chip housing also has two regions which extend to opposite sides beyond the edges of the semiconductor chip. As viewed from the plan view, the semiconductor chip is mounted on the chip housing in a position which lies precisely in the center between the two arrays or arrangements of contact connections. However, the contact connections are generally arranged on the underside, whereas the semiconductor chip is generally arranged on the top side of the BGA housing.
When electrically driving a plurality of semiconductor components, in particular a plurality of housed semiconductor chips, it is customary to conduct all signals for driving or reading from the semiconductor components through all the semiconductor components. Thus, in the case of, for example, four semiconductor components connected in series, the signals for all four semiconductor components are forwarded with the aid of the same lines. Said lines also comprise line sections within those semiconductor components themselves.
The signals to be communicated to the semiconductor components comprise, inter alia, control commands, address commands and data values to be stored. These signals are referred to hereinafter as first signals. Further signals, which comprise in particular the data values to be read out or data values that have been read out from the semiconductor components, are referred to hereinafter as second signals. The first and second signals may additionally in each case also comprise at least one clock signal which supports the temporal coordination during the high-frequency communication of said signals.
First lines are usually provided for the communication of the first signals, along which first lines the first signals are routed through the semiconductor components connected in series, beginning with a first semiconductor component and ending with a last semiconductor component of the series circuit, from which they are conducted further to the printed circuit board of the superordinate electronic unit (for example of the memory module). For the second signals, by contrast, second lines are provided, with the aid of which the data values to be read out are likewise routed through all the semiconductor components connected in series.
The order in which the second signals pass through the semiconductor components connected in series may be identical to the order in which the first signals pass through the semiconductor components, may be identical to the order in which the second signals pass through the semiconductor components, or may deviate from said order. If the order for the first and second signals is identical in each case, this is called a PLF (parallel loop forward) interconnection. However, if the second signals or the data values that have been read out pass through the interconnected semiconductor components in a different order, in particular in a reverse order, with respect to the first signals, this is called a loop back interconnection.
Semiconductor components are usually embodied for one of these two types of communication of the first and second signals, with the result that a chip housing developed for a loop forward configuration must normally be used for this configuration. If such a chip housing (and the semiconductor component formed using said chip housing and a semiconductor chip) is intended to be used for a loop back configuration, subsequent constructive changes are necessary for at least one of the chip housings that are to be interconnected. This holds true particularly when a plurality of housings of the semiconductor chips are to be stacked one on top of another. In the case of a chip housing for a semiconductor component that is to be interconnected in accordance with the loop forward configuration, in particular the second lines, that is to say the lines for communicating the data values read out, lead on the output side to the top side of the chip housing. Since contact is made with the chip housing from the underside, however, the data values read out have to be forwarded from the top side to the underside. This is done with the aid of contact hole fillings or other conductive structures that reach from the top side as far as the underside of the chip housing. Such conductive connections may already be contained in a conventional chip housing for the loop forward configuration. In order, however, to prepare said chip housing for a loop back configuration, that contact on the top side which is conductively connected to a contact connection on the underside of the chip housing and would therefore be suitable for feeding back the data values downward, must subsequently be conductively connected to an output connection of the semiconductor chip. For this purpose, a conductive connection between this conducting line path and a corresponding chip-side connection of the chip housing subsequently has to be prepared on the top side.
Consequently, conventional semiconductor components cannot be used for a loopback configuration without subsequent constructive changes.
Apart from this additional outlay, a further disadvantage initially consists in the fact that the above-described additional conductive connections from the top side to the underside are actually necessary for feeding back the data values. Although the requisite contact connections on the underside are already present within the arrangements of contact connections, they increase the basic surface to be reserved for electrically driving the semiconductor components.
In order to be able to feed back the data values in accordance with the loopback configuration, it is necessary, therefore, for additional contact connections on the underside of the chip housing to be through-connected upward, thereby increasing the outlay in the mounting of the chip housings. Moreover, the contact connections that are to be additionally utilized for a subsequently provided loopback configuration for feeding back the data values read out enlarge the contact surface arrays not only of the chip housings themselves but also the regions of the electronic printed circuit board which are to be reserved for making contact with the semiconductor components. This additionally restricts the possibilities for the design of the conducting line courses on the part of the printed circuit board which drive the semiconductor components.